1. Field of the Invention
This invention relates generally to apparatus for error correction and specifically to error correction apparatus suitable for use in a complex data transmission system involving arrangement and rearrangement of data sequences on a known time-base.
2. Description of the Prior Art
It has been previously proposed to use a so-called cross-interleave technique in a data transmission system that is effective in correcting burst errors (for example, see Japanese patent applications Nos. 47247/78, 67608/80 and 84428/80). According to this cross-interleave technique, one word contained in each of a number of pulse code modulated (PCM) data sequences in a first arrangement state is placed on a plurality of channels and is fed to a first error correction encoder, wherein a first check word series is generated. The first check word series and the PCM data sequences on a plurality of channels are converted to a second arrangement state, and one word contained in each of the newly arranged channels is supplied to a second error correction encoder, wherein a second check word series is generated. By means of the foregoing, double interleaving processing, involving the rearrangement of a known arrangement state, is carried out in each word unit. The purpose of the interleaving technique is to disperse the check words and the PCM data contained in the common error correction block and then to transmit the same, thereby reducing the number of error words within the plural words contained in a common error correction block when the transmitted signals are reconverted to the original arrangement state at the receiving side. In other words, when burst error occurs upon transmission, such burst error can be dispersed among the plurality of channels of the system. Doubling the above-described interleaving processing allows the first and second check words to form independent error correction blocks, so that even when an error can not be corrected by one check word, such error can be corrected by the other check word, thereby expanding the error correction ability provided by the interleaving processing.
The apparatus to accomplish the above-described error correction for such data transmission system is required to perform complex calculation processing for error correction and de-interleaving processing (rearrangement). Accordingly, constructing the error correction apparatus by random discrete logic devices requires many complex interconnections. Moreover, to integrate the logic circuit into a large-scale integrated circuit (LSI) is very disadvantageous due to the requirement for an excessively large surface area made necessary by the complexity of the circuit.
On the other hand, in using a microprocessor or apparatus having a microprogram system, and when the calculation processing is quite complicated, it is considered advantageous to arrange function blocks for the calculation processing in parallel and to control these function blocks by a so-called horizontal microprogram system. Thus, the respective function blocks simultaneously carry out the calculation processings, thereby providing much faster calculation processings.
In such calculation apparatus using a microprogram system, it is desired to control simultaneously the function blocks as much as possible so that calculation processing can be executed with increased efficiency. However, to control a number of function blocks simultaneously, the number of bits in one step has to be increased, requiring a corresponding increase in the capacity of the memory for memorizing the microprogram, and necessitating an increase in the size of the read-only memory (ROM).